The present invention relates to integrated circuits and more particularly to a clock buffer that shares a clock-gated pull-up transistor for reduced power consumption and reduced precharge time.
Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. Decreasing the size of the processor and reducing its power consumption lowers the cost and improves the reliability of the processor. Processor designers employ many different techniques to decrease processor size and to reduce power consumption to create less expensive and more robust computers for consumers.
Typically, for a given frequency and transistor size, circuits having more transistors that are actively switched tend to consume more power than circuits having fewer transistors that are actively switched. Therefore, designers strive to reduce the number and size of actively switched transistors, such as those that are gated (or clocked) by a high frequency clock signal. These transistors include, for example, clock buffer transistors having gates coupled to a clock signal line.
Unfortunately, to increase processor performance, the total transistor count of the processor typically must increase. Thus, there is a constant struggle between the need for processor designers to increase the performance of a processor and the need to reduce the number and size of clocked transistors in the processor to reduce power consumption. The present invention addresses this struggle.